Search Algorithms for Satisfiability Problems in Combinational Switching Circuits
نویسندگان
چکیده
SEARCH ALGORITHMS FOR SATISFIABILITY PROBLEMS IN COMBINATIONAL SWITCHING CIRCUITS by João Paulo Marques da Silva Chair: Karem A. Sakallah A number of tasks in computer-aided analysis of combinational circuits, including test pattern generation, timing analysis, delay fault testing and logic verification, can be viewed as particular formulations of the satisfiability problem (SAT). The first purpose of this dissertation is to describe a configurable search-based algorithm for SAT that can be used for implementing different circuit analysis tools. Several methods for reducing the amount of search are detailed and integrated into a general algorithmic framework for solving SAT. Special emphasis is given to the description of methods for diagnosing the causes of conflicts that may be identified while searching for a solution to each instance of SAT. These methods allow the implementation of nonchronological backtracking, conflict identification based on equivalence relations and logic value assertions derived from conflicts. Path sensitization in combinational circuits is often used to solve test pattern generation, timing analysis and delay fault testing problems. While path sensitization can be cast as an instance of SAT, such an approach can conceal desirable structural properties of the problem and may lead to exponential size representations. Another purpose of this dissertation is to introduce a new model for path sensitization that permits modeling test pattern generation and timing analysis with linear size representations. In addition, this formulation for path sensitization permits the adaptation of all the pruning methods developed for the general SAT problem. The proposed SAT algorithms and path sensitization model form an initial kernel for the development of tools for the analysis of combinational circuits. Their practical applicability is supported by experimental results obtained with test pattern generation and timing analysis tools. SEARCH ALGORITHMS FOR SATISFIABILITY PROBLEMS IN COMBINATIONAL SWITCHING CIRCUITS
منابع مشابه
Algorithms for Satisfiability in Combinational Circuits Based on Backtrack Search and Recursive Learning
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation (EDA). It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover, Boolean Satisfiability is also in the core of algorithms for solving Binate Covering Problems. This paper starts by describing how B...
متن کاملAlgorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalence checking and circuit delay computation, among many other problems. Moreover, Boolean Satisfiability is in the core of algorithms for solving Binate Covering Problems. This paper describes how Boolean Satisfiability ...
متن کاملCombinational test generation using satisfiability
We present a robust and efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, TEGUS, has the following features. We choose a form for the test set characteristic equation which minimizes its size. The simplified equation is solved by an algorithm for SAT using simple, but powerful, greedy heuristics, ordering the variables using depth-fi...
متن کاملAND/OR reasoning graphs for determining prime implicants in multi-level combinational networks
This paper presents a technique to determine prime implicants in multi-level combinational networks. The method is based on a graph representation of Boolean functions called AND/OR reasoning graphs. This representation follows from a search strategy to solve the satisfiability problem that is radically different from conventional search for this purpose (such as exhaustive simulation, backtrac...
متن کاملLow Power March Memory Test Algorithm for Static Random Access Memories (TECHNICAL NOTE)
Memories are most important building blocks in many digital systems. As the Integrated Circuits requirements are growing, the test circuitry must grow as well. There is a need for more efficient test techniques with low power and high speed. Many Memory Built in Self-Test techniques have been proposed to test memories. Compared with combinational and sequential circuits memory testing utilizes ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1995